Integrated Circuits Overview

Principles

Definition

Integrated circuits is the academic discipline concerned with the theoretical principles, design methodologies, fabrication technologies, and practical applications of complex electronic circuits integrated onto a single semiconductor chip. This field is crucial for advancing modern electronics by enabling the miniaturization, increased complexity, and enhanced performance necessary for contemporary computing and communication systems.

Ontological type

Fabrication Technologies

Core Design Methodologies

Architectures and Topologies

Key developments

Key Figures

MOS Scaling and CMOS era

R.H. Dennard [1] was a pivotal figure in the MOS scaling and CMOS era, with stints at the University of California, Santa Barbara [3] and the Georgia Institute of Technology [4]. His design work on Design of ion-implanted MOSFET's with very small physical dimensions [5] showcased how ion implantation and deep-submicron scaling could push performance and density, shaping the submicron MOS transistors central to the era. Phillip E. Allen [2] is associated with innovations in CMOS design, with affiliations including the University of California, Santa Barbara [3] and the Georgia Institute of Technology [4]. His 1988 paper CMOS analog circuit design [6] helped codify design methodologies for CAD-driven yield and reliability in very-large-scale integration, underpinning the practical adoption of dense CMOS networks in the MOS scaling era.

Silicon Photonics Maturation era

Gordon E. Moore [1] is a defining figure in semiconductor scaling during the silicon IC era, shaping how institutions across academia and industry pursued component density. In the 1998 paper Cramming More Components Onto Integrated Circuits [5], Moore [1] articulates the ongoing trend of increasing transistor density and integration, a contribution that underpinned the era's drive toward dense, low-latency photonic-electronic subsystems. Stephen Y. Chou [2] has been associated with Stanford University [3] and Princeton University [4] during this era. His key contribution, Imprint Lithography with 25-Nanometer Resolution [6], enabled the dense patterning required for silicon photonics integration, helping translate device-level advances into high-bandwidth interconnects.

Wafer-Scale Programmable Photonics era

John E. Bowers [1], associated with Harvard University [3] and Johns Hopkins University [4], was a leading figure in the Wafer-Scale Programmable Photonics era during 2015–2024. His contributions include the fully integrated hybrid silicon two dimensional beam scanner [7], the heterogeneous Silicon Photonic Integrated Circuits [8], and silicon nitride passive and active photonic integrated circuits: trends and prospects [9], which collectively enabled scalable on-chip reconfiguration and manufacturing essential to the era. Hao-Chung Kuo [2], affiliated with University of California, Berkeley [5] and Xiamen University [6], contributed to the same Wafer-Scale Programmable Photonics landscape during this era. His work on Mini-LED and Micro-LED: Promising Candidates for the Next Generation Display Technology [10] highlighted scalable, high-brightness display sources compatible with wafer-scale photonic integration.